ESMT
F49L160UA/F49L160BA
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and backward- compatible for the specified flash
device families. Flash vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is ready to array data. The system can read CFI information at
the address given in Tables 8-10 in word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the addresses given in Tables 8-10. The system must write the reset
command to return the device to the autoselect mode.
Table 8 CFI Query Identification String
Addresses
(Word Mode) (Byte Mode)
Address
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 9 System Interface String
Addresses
(Word Mode) (Byte Mode)
Address
Data
Description
VCC Min. (write/erase)
D7~D4 : volt, D3~D0 : 100 millivolt
VCC Max. (write/erase)
D7~D4 : volt, D3~D0 : 100 millivolt
1Bh
1Ch
36h
38h
0027h
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N μs
Typical timeout for Min. size buffer write 2N μs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N word times typical
Max. timeout for buffer write 2N word times typical
Max. timeout per individual block erase 2N word times typical
Max. timeout per full chip erase 2N word times typical (00h = not supported)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.8 19/50
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
