ESMT
F49L160UA/F49L160BA
Table 9 System Interface String
Addresses
(Word Mode) (Byte Mode)
Address
Data
Description
VCC Min. (write/erase)
D7~D4 : volt, D3~D0 : 100 millivolt
VCC Max. (write/erase)
D7~D4 : volt, D3~D0 : 100 millivolt
1Bh
1Ch
36h
38h
0027h
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N μs
Typical timeout for Min. size buffer write 2N μs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N word times typical
Max. timeout for buffer write 2N word times typical
Max. timeout per individual block erase 2N word times typical
Max. timeout per full chip erase 2N word times typical (00h = not supported)
Table 10 Device Geometry Definition
Addresses
(Word Mode) (Byte Mode)
Address
Data
Description
27h
4Eh
0015h
Device Size = 2N byte
28h
29h
2Ah
2Bh
50h
52h
54h
56h
0002h
0000h
0000h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
0000h
0000h
0004h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h
0000h
001Eh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2006
Revision: 1.3 20/51
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
