EFST
preliminary
F49L004UA / F49L004BA
Figure 22. Toggle Bit Timing Waveforms (During Embedded Algorithms)
tR C
VA
VA
Addr es s
VA
VA
tAC C
tC E
C E
tC H
t O E
OE
W E
tO E H
tD F
tO H
H i gh - Z
V
a i l d
S t a t u s
V a i l d
S t a t u s
V a i l d
D a t a
V a i l d
D a t a
DQ6/DQ 2
( s e c o n d r e a d )
( f i r s t r e a d )
( s t o p s t o g g l i n g )
tB U S Y
RY/B Y
Notes :
VA = Valid Address; not required for DQ6. Figure shows first status cycle after command sequence, last status
read cycle, and array data read cycle.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 39/46