EFST
7.1 Device operation
preliminary
F49L004UA / F49L004BA
7. FUNCTIONAL DESCRIPTION
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to
machine. The state machine
function of the device.
F49L004BA features various
Table 3.
the internal state
outputs dictate the
The F49L004UA/
bus operations as
Table 3. F49L004UA/F49L004BA Operation Modes Selection
ADDRESS
DESCRIPTION
CE
OE WE
RESET
A18 A12
|
|
A13 A10
A9
A8
|
A7
X
AIN
AIN
X
X
A6
A5
|
A2
A1 A0
DQ0~DQ7
Reset(3)
Read
Write
Output Disable
Standby
Sector Protect(2)
Sector Unprotect(2)
Temporary sector unprotect
Auto-select
Notes:
X
L
L
L
V
CC
±
0.3V
L
L
X
X
L
H
H
X
H
H
X
X
H
L
H
X
L
L
X
L, Vss±
0.3V(4)
H
H
H
V
CC
±
0.3V
V
ID
V
ID
V
ID
See Table 4
SA
SA
X
X
X
X
High Z
Dout
DIN
High Z
High Z
L
H
X
X
H
H
L
L
DIN
DIN
DIN
X
X
AIN
1.
L= Logic Low = V
IL
, H= Logic High = V
IH
, X= Don't Care, SA= Sector Address, V
ID
=11.5V to 12.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3.
RESET
pin for 40-TSOP package type only.
4. See “Reset Mode” section.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2
5/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
