EFST
preliminary
F49L004UA / F49L004BA
10.3 Hardware Reset Operation
Table 13. AC CHARACTERISTICS (for 40-pin TSOP package type)
Symbol
Description
All Speed Options
Unit
Pin Low (During Embedded Algorithms)
RESET
TREADY1
Max
Max
20
us
to Read or Write (See Note)
Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
RESET
TREADY2
500
ns
Pulse Width (During Embedded Algorithms)
RESET
Min
Min
Min
500
50
0
ns
ns
ns
TRP
TRH
TRB
High Time Before Read(See Note)
RESET
RY/
Recovery Time(to
,
go low)
BY
CE OE
Notes :
Not 100% tested
Figure 23.
Timing Waveform (for 40-pin TSOP package type)
RY/B Y
CE, O E
RE S E T
tR H
tR P
tR e a d y 2
Reset T i mi ng NO T dur i ng Au tom at i c Al gor i th m s
tR e a d y 1
RY/B Y
tR B
CE, O E
RE S E T
tR P
Reset T im in g dur i ng A ut om ati c A lgori th m s
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 40/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
