EFST
preliminary
F49L004UA / F49L004BA
7.4 More Device Operations
Hardware Data Protection
Write cycles are inhibited by holding any one of
= VIL,
and
OE
= VIH. To initiate a write cycle,
= VIH or
WE
must be a logical zero while
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware
data protection measures prevent accidental erasure or
programming, which might otherwise be caused by
CE
WE
CE
is a logical one.
OE
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
its VCC and GND.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept
Power-Up Sequence
The device powers up in the Read Mode. In addition, the
memory contents may only be altered after successful
completion of the predefined command sequences.
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until VCC is greater than
V
LKO. The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC is
greater than VLKO
Power-Up Write Inhibit
.
If
=
= VIL and
= VIH during power up, the
OE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
Write Pulse "Glitch" Protection
WE
reading array data on power-up.
Noise pulses of less than 5 ns (typical) on
WE
,
or
OE CE
do not initiate a write cycle.
Logical Inhibit
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 16/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
