EFST
4.1 40-pin TSOP I
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
preliminary
F49L004UA / F49L004BA
4. PIN CONFIGURATIONS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
NC
NC
A10
DQ 7
DQ 6
DQ 5
DQ 4
VCC
VCC
NC
DQ 3
DQ 2
DQ 1
DQ 0
OE
VSS
CE
A0
4.2 32-pin PLCC
A15
3
A16
A18
V
CC
A17
A12
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ 0
WE
2
1 32 31 30
5
6
7
8
9
10
11
12
13
14 15 16 1 7 18 19 2 0
DQ 1
DQ 2
GND
DQ 3
DQ 4
DQ 5
DQ 6
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ 7
4.3 Pin Description
Symbol
A0~A18
DQ0~DQ7
CE
OE
WE
RESET
RY/ BY
V
CC
GND
Pin Name
Address Input
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy
Power Supply
Ground
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
To activate the device when CE is low.
To gate the data output buffers.
To control the Write operations.
Hardware Reset Pin/Sector Protect Unprotect (for 40-TSOP)
To check device operation status(for 40 TSOP)
To provide power
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2
2/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
