EFST
F49B002UA
7.4 More Device Operations
Hardware Data Protection
Logical Inhibit
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
Write cycles are inhibited by holding any one of
=
OE
V ,
IL
= V or
= V . To initiate a write cycle,
WE
CE
IH
IH
and
must be a logical zero while
is a
OE
WE
CE
logical one.
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between
Low VCC Write Inhibit
its V
and GND.
CC
When V
is less than VLKO, the device does not
CC
accept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
Power-Up Sequence
device resets. Subsequent writes are ignored until V
CC
The device powers up in the Read Mode. In addition,
the memory contents may only be altered after
successful completion of the predefined command
sequences.
is greater than V . The system must provide the
LKO
proper signals to the control pins to prevent
unintentional writes when V
is greater than V
.
CC
LKO
Power-Up Write Inhibit
Write Pulse "Glitch" Protection
Noise pulses of less than 15 ns (typical) on
or
If
=
= V and
= V during power up,
OE
IH
WE
the device does not accept commands on the rising
edge of The internal state machine is
CE
CE
IL
do not initiate a write cycle.
WE
.
WE
automatically reset to reading array data on power-up.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
10/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
