ESMT
INSTRUCTIONS
(Preliminary)
F25S04PA
Instructions are used to Read, Write (Erase and Program), and
configure the F25S04PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
significant bit. CE must be driven low before an instruction is
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Operation
Read
Fast Read
Fast Read Dual
11,12
Output
Sector Erase
4
(4K Byte)
Block Erase
4,
(64K Byte)
Chip Erase
Page Program (
PP
)
Read Status Register
(
RDSR
)
6
Write Status Register
(
WRSR
)
Write Enable (
WREN
)
9
Write Disable (
WRDI
)
Deep Power Down (
DP
)
Release from Deep
Power Down (
RDP
)
Read Electronic
7
Signature (
RES
)
Jedec Read ID
(
JEDEC-ID
)
8
Read ID (
RDID
)
10
50
MHz
~
Bus Cycle
1~3
1
2
3
4
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
33
MHz
03H Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
X
0BH Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
X
Max.
Freq
3BH
20H
D8H
60H /
C7H
02H
05H
01H
100
MHz
06H
04H
B9h
ABH
ABH
9FH
90H
A
23
-A
16
A
15
-A
8
A
7
-A
0
-
-
-
D
IN0
-
-
-
-
-
-
X
-
X
X
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z
-
-
-
-
-
-
5
S
OUT
D
OUT0
X
X
-
-
-
Hi-Z
-
-
-
-
-
-
12H
-
8CH
12H
-
-
-
D
IN1
-
-
-
-
-
-
-
-
X
X
6
S
IN
X
X
S
OUT
D
OUT1
D
OUT0
-
-
-
Hi-Z
-
-
-
-
-
-
-
-
12H
8CH
N
S
IN
S
OUT
X
X
-
-
-
cont.
cont.
-
-
-
D
OUT0~1
cont.
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
D
IN
-
-
-
-
X
X
00H
D
OUT
Hi-Z
-
-
-
-
X
8CH
Hi-Z
-
-
-
-
-
-
X
X
00H
-
-
-
-
-
-
X
20H
Hi-Z
-
-.
-
-
-
-
X
X
00H
01H
-
-
-
-
-
-
X
13H
Hi-Z
Hi-Z
Up to
256 Hi-Z
bytes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Operation: S
IN
= Serial In, S
OUT
= Serial Out, Bus Cycle 1 = Op Code
X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
One bus cycle is eight clock periods.
Sector Earse addresses: use A
MS
-A
12
, remaining addresses can be V
IL
or V
IH
Block Earse addresses: use A
MS
-A
16
, remaining addresses can be V
IL
or V
IH
To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as
memory capacity.
The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
Elite Semiconductor Memory Technology Inc.
Publication Date:
May
2009
Revision:
0.2
9/34
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
