ESMT
(Preliminary)
F25S04PA
VCC
VCC (max)
Program, Erase and Write command is ignored
CE must track VCC
VCC (min)
Read command
is allowed
T
VSL
Device is fully
accessible
Reset
State
VWI
T
PUW
Time
Figure 24: Power-Up Timing Diagram
Table 13: Power-Up Timing and VWI Threshold
Unit
Parameter
Symbol
Min.
10
1
Max.
TVSL
TPUW
VWI
us
ms
V
VCC(min) to CE low
Time Delay before Write instruction
10
2
Write Inhibit Threshold Voltage
1
Note: These parameters are characterized only.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 0.2 27/34