ESMT
F25S004A
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A
Chip-Erase instruction will be ignored if any of the memory area
is protected. Prior to any Write operation, the Write-Enable
60H or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the software status
register or wait TCE for the completion of the internal self-timed
Chip-Erase cycle.
(WREN) instruction must be executed. CE must remain active
low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command,
See Figure 11 for the Chip-Erase sequence.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
FIGURE 11 : CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
and remain low until the status data is read.
Read-Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE
See Figure 12 for the RDSR instruction sequence.
CE must be driven low before the RDSR instruction is entered
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK MODE1
05
SI
MSB
HIGH IMPENANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status
Register Out
Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.1 17/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
