ESMT
F25S004A
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch
bit and AAI bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
04
MSB
HIGH IMPENANCE
SO
Figure 14 : WRITE DISABLE (WRDI) SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.1
18/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
