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F25L32QA-86PAG 参数 Datasheet PDF下载

F25L32QA-86PAG图片预览
型号: F25L32QA-86PAG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有32兆位串行闪存,配有双核和四 [3V Only 32 Mbit Serial Flash Memory with Dual and Quad]
分类和应用: 闪存
文件页数/大小: 42 页 / 484 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
(Preliminary)  
F25L32QA  
„ PIN DESCRIPTION  
Symbol  
Pin Name  
Functions  
To provide the timing for serial input and output operations  
SCK  
Serial Clock  
To transfer commands, addresses or data serially into the device. Data is  
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO  
pin to transfer commands, addresses or data serially into the device on the  
rising edge of SCK and read data or status from the device on the falling edge  
of SCK(for Dual/Quad mode).  
Serial Data Input /  
Serial Data Input Output 0  
SI / SIO0  
To transfer data serially out of the device. Data is shifted out on the falling edge  
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,  
addresses or data serially into the device on the rising edge of SCK and read  
data or status from the device on the falling edge of SCK (for Dual/Quad  
mode).  
Serial Data Output /  
Serial Data Input Output 1  
SO / SIO1  
Chip Enable  
CE  
To activate the device when CE is low.  
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status  
register. / Bidirectional IO pin to transfer commands, addresses or data serially  
into the device on the rising edge of SCK and read data or status from the  
device on the falling edge of SCK (for Quad mode).  
Write Protect /  
Serial Data Input Output 2  
WP / SIO2  
To temporality stop serial communication with SPI flash memory without  
resetting the device. / Bidirectional IO pin to transfer commands, addresses or  
data serially into the device on the rising edge of SCK and read data or status  
from the device on the falling edge of SCK (for Quad mode).  
Hold /  
HOLD / SIO3  
Serial Data Input Output 3  
VDD  
VSS  
Power Supply  
Ground  
To provide power.  
„ FUNCTIONAL BLOCK DIAGRAM  
Page Address  
Latch / Counter  
Memory  
Array  
High Voltage  
Generator  
Page Buffer  
Y-Decoder  
Status  
Register  
Byte Address  
Latch / Counter  
Command and Conrol Logic  
Serial Interface  
CE  
SCK  
SO  
(SIO  
WP  
(SIO  
HOLD  
(SIO3)  
SI  
(SIO0)  
1
)
2
)
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2009  
Revision: 0.2 3/42  
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