ESMT
(Preliminary)
F25L32QA
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L32QA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instruction
Bus Cycle 1~3
4
Max.
Freq
Operation
1
2
3
5
6
N
SIN SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT
Read
Fast Read
33 MHz 03H Hi-Z A23-A16 Hi-Z
0BH Hi-Z A23-A16 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
X
X
DOUT0
X
X
X
X
DOUT1
DOUT0
X
X
cont.
cont.
cont.
-
cont.
-
Fast Read Dual Output12,13
Fast Read Dual I/O12, 14
Fast Read Quad
3BH
BBH
A23-A16
A23-A8
A15-A8
A7-A0
DOUT0~1
A7-A0, M7-M0
DOUT0~1
cont.
-
6BH
EBH
A23-A16
A15-A8
A7-A0
X
DOUT0~3
-
-
-
Output12, 15
Fast Read Quad I/O12, 16
Sector Erase4 (4K Byte)
Block Erase4, (64K Byte)
A23-A0, M7-M0
X, DOUT0~1
DOUT2~6
cont.
20H Hi-Z A23-A16 Hi-Z
D8H Hi-Z A23-A16 Hi-Z
60H /
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
-
-
-
-
-
-
-
-
-
-
Chip Erase
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
02H Hi-Z A23-A16 Hi-Z
32H A23-A16
ADH Hi-Z A23-A16 Hi-Z
Up to
Page Program (PP)
Quad Page Program17
A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z 256 Hi-Z
bytes
Up to 256
A15-A8
A7-A0
DIN0~3
DIN4~7
bytes
Auto Address Increment
word programming5 (AAI)
Mode Bit Reset18
Deep Power Down (DP)
Read Status Register-1
(RDSR-1) 6
50MHz
~
A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z
-
-
FFH Hi-Z
B9h Hi-Z
FFH
-
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DOUT
(S7-S0)
DOUT
(S15-S8)
05H Hi-Z
35H Hi-Z
50H Hi-Z
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Read Status Register-2
(RDSR-2) 6
100MHz
Enable Write Status
Register (EWSR) 7
Write Status Register
(WRSR) 7
-
DIN
(S7-S0)
-
DIN
(S15-S8)
-
01H Hi-Z
06H Hi-Z
04H Hi-Z
Hi-Z
Hi-Z
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Enable (WREN) 10
Write Disable (WRDI)/ Exit
secured OTP mode
Enter secured OTP mode
(ENSO)
-
-
-
-
-
-
-
-
-
B1H
Hi-Z
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Release from Deep Power
Down (RDP)
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
-
-
-
-
-
-
-
Read Electronic Signature
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15H
35H
75H
(RES) 8
RES in secured OTP mode
& not lock down
RES in secured OTP mode
& lock down
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 0.2 12/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
