ESMT
F25L32PA
TABLE 12: LATCH UP CHARACTERISTIC
Symbol
Parameter
Latch Up
Minimum
Unit
Test Method
JEDEC Standard 78
1
ILTH
100 + IDD
mA
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Unit
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
10
10
1
TPU-WRITE
µs
TABLE 14: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
12 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 15: AC OPERATING CHARACTERISTICS
Normal 33 MHz
Fast 50 MHz
Fast 86 MHz
Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
FCLK
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
33
50
86
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSCKH
TSCKL
13
13
5
9
9
7
7
5
5
1
TCES
5
5
5
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
5
1
TCHS
5
5
5
5
1
TCHH
5
5
5
5
TCPH
TCHZ
TCLZ
TDS
100
100
100
100
9
9
9
9
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
TDH
Data In Hold Time
THLS
THHS
THLH
THHH
THZ
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
HOLD High Hold Time
HOLD Low to High-Z Output
9
9
9
9
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0 28/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
