ESMT
F25L32PA
PIN DESCRIPTION
Symbol
SCK
Pin Name
Functions
Serial Clock
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard mode). / Bidirectional IO pin to
transfer commands, addresses or data serially into the device on the rising
edge of SCK and read data or status from the device on the falling edge of
SCK(for Dual mode).
Serial Data Input /
Serial Data Input Output 0
SI / SIO0
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual mode).
Serial Data Output /
Serial Data Input Output 1
SO / SIO1
Chip Enable
Write Protect
CE
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register.
WP
To temporality stop serial communication with SPI flash memory without
resetting the device.
Hold
HOLD
VDD
VSS
Power Supply
Ground
To provide power.
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
Memory
Array
High Voltage
Generator
Page Buffer
Y-Decoder
Status
Register
Byte Address
Latch / Counter
Command and Conrol Logic
Serial Interface
CE
SCK
SO
(SIO
WP
HOLD
SI
(SIO0)
1
)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0 3/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
