ESMT
F25L32PA
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the BUSY bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 19 for the Chip Erase sequence.
instruction must be executed. CE must remain active low for
the duration of the Chip-Erase instruction sequence. The Chip
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
Figure 19: Chip Erase Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation. When a Write
operation is in progress, the BUSY bit may be checked before
sending any new commands to assure that the new commands
are properly received by the device.
CE must be driven low before the RDSR instruction is entered
and remain low until the status data is read. The RDSR-1
instruction code is “05H” for Status Register. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 20
for the RDSR instruction sequence.
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK MODE0
05
SI
MSB
HIGH IMPEDANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status Register Data Out
Figure 20: Read Status Register (RDSR) Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0 20/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
