ESMT
F25L32PA
Mode Bit Reset
Mode bits [M7 –M0] are issued to further reduce instruction
overhead for Fast Read Dual I/O operation. If [M7 –M0] = “AxH”,
the next Fast Read Dual I/O instruction doesn’t need the
command code.
However, the device doesn’t have a hardware reset pin, so if
[M7 –M0] = “AxH”, the device will not recognize any standard SPI
instruction. After a system reset, it is recommended to issue a
Mode Bit Reset instruction first to release the status of [M7 –M0] =
“AxH” and allow the device to recognize standard SPI instruction.
See Figure 16 for the Mode Bit Reset instruction.
If the system controller is reset during operation, it will send a
standard instruction (such as Read ID) to the Flash memory.
Mode bit Reset for Dual I/O
CE
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
MODE3
MODE0
SCK
SIO0
SIO1
FF
FF
Note: To reset mode bits during Dual I/O operation, sixteen clocks are needed to shift in command code “FFFFH”.
Figure 16: Mode Bit Reset Instruction
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0 18/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
