ESMT
F25L32PA
HOLD OPERATION
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
when the HOLD signal’s rising edge coincides with the SCK
active low state.
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 23 for Hold
timing.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
The HOLD function is only available for Standard and Dual SPI
operation.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
SCK
HOLD
Hold
Active
Active
Active
Hold
Figure 1: HOLD Condition Waveform
WRITE PROTECTION
The device provides software Write Protection.
Table 4: Conditions to Execute Write-Status- Register
(WRSR) Instruction
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See Table
4 for Block-Protection description.
BPL
1
Execute WRSR Instruction
Not Allowed
WP
L
L
0
Allowed
Write Protect Pin ( WP )
H
X
Allowed
The Write-Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0 11/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
