ESMT
F25L32QA (2S)
Revision History
Revision
Date
Description
0.1
2011.01.27
Original
1. Ordering information : add 2S
2. Remove Byte program time
3. Discriminate between status register -1 and status
register -2
4. Modify WSON 6x5mm dimension : D2 2.5(min),
2.60(norm), 2.70(max) and E2 2.10(min), 2.20(norm),
2.30(max)
1. Add 32KB Block into sector address table
2. Delete SOIC (150mil) and PDIP package
3. Correct WRSR, Status Register-2 and block protection
table
0.2
0.3
2011.03.03
2011.07.04
4. Add RDSR-2
5. Modify the specification of TCE(max)
1. Correct command code of RDSR-2 in device operation
instruction table
2. Correct WRSR command
Correct Status Register-2 in Software Status Register
table
0.4
0.5
2011.09.14
2011.09.15
0.6
1.0
1.1
1.2
1.3
2011.10.13
2012.02.20
2012.04.18
2012.07.20
2012.09.21
Modify minimum voltage from 2.7V to 2.65V
Delete “Preliminary”
Modify the range of TA
Modify 100MHz to 104MHz for speed grade -100
Modify Ambient Operating Temperature
1. Modify the specification of TCPH
2. Correct the description of Block Protection, Block
Protection Lock-Down
1.4
2012.12.03
1.5
1.6
1.7
2013.03.28
2013.04.17
2013.04.23
Modify normal read from 33MHz to 50MHz
Correct max. value of TWHSL and TSHWL to min. value
Add 8 lead SOIC (150 mil) package
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7 50/51
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
