ESMT
F25L32QA (2S)
Table 3: F25L32QA Block Protection Table
Status Register Bit
Protected Memory Area
Protection Level
BP3
0
BP2
0
BP1
0
BP0
0
64KB Block Range
None
Address Range
None
0
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
0
0
0
1
Block 63
3F0000H – 3FFFFFH
3E0000H – 3FFFFFH
3C0000H – 3FFFFFH
380000H – 3FFFFFH
300000H – 3FFFFFH
200000H – 3FFFFFH
000000H – 3FFFFFH
000000H – 3FFFFFH
000000H – 1FFFFFH
000000H – 2FFFFFH
000000H –37FFFFH
000000H – 3BFFFFH
000000H – 3DFFFFH
000000H – 3EFFFFH
000000H – 3FFFFFH
0
0
1
0
Block 62~63
Block 60~63
Block 56~63
Block 48~63
Block 32~63
Block 0~63
Block 0~63
Block 0~31
Block 0~47
Block 0~55
Block 0~59
Block 0~61
Block 0~62
Block 0~63
0
0
1
1
0
1
0
0
Upper 1/4
0
1
0
1
Upper 1/2
0
1
1
0
All Blocks
All Blocks
Bottom 32/64
Bottom 48/64
Bottom 56/64
Bottom 60/64
Bottom 62/64
Bottom 63/64
All Blocks
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Block Protection (BP3, BP2, BP1, BP0)
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”.
BP3, BP2, BP1 and BP0 bits as long as WP is high or the
Block- Protection-Look (BPL) bit is 0. Chip Erase can only be
executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory
default setting for Block Protection Bit (BP3 ~ BP0) is 0.
Block Protection Lock-Down (BPL)
Program / Erase Suspend Status (SUS)
Quad Enable (QE)
The Suspend Status bit is a read only bit in the status register
that is set to 1 after executing a Program / Erase Suspend (75H)
instruction.
The SUS Status bit is cleared to 0 by Program / Erase Resume
(7AH) instruction as well as a power-down, power-up cycle.
When the Quad Enable bit is reset to “0” (factory default), WP
and HOLD pins are enabled. When QE pin is set to “1”, Quad
SIO2 and SIO3 are enabled. (The QE should never be set to “1”
during standard and Dual SPI operation if the WP and HOLD
pins are tied directly to the VDD or VSS.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7
16/51
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
