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F25L16PA-50PG 参数 Datasheet PDF下载

F25L16PA-50PG图片预览
型号: F25L16PA-50PG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有16兆位串行闪存,配有双 [3V Only 16 Mbit Serial Flash Memory with Dual]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 33 页 / 471 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L16PA  
Note:  
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code  
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous  
3. One bus cycle is eight clock periods.  
4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH  
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH  
5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be  
programmed.  
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .  
7. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in  
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR  
instruction to make both instructions effective.  
8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .  
9. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 15H as  
memory capacity.  
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each  
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both  
instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can  
reset WREN.  
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.  
12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.  
13. Dual output data:  
IO  
IO  
0
= (D  
6
, D  
4
, D  
2
, D  
0
), (D  
6
, D  
4
, D  
2
, D  
0
)
)
1
= (D  
7
, D5  
, D3  
, D1  
), (D  
7
, D5  
, D3  
, D1  
DOUT0  
DOUT1  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jul. 2009  
Revision: 1.4 10/33