ESMT
F25L16PA
ERASE AND PROGRAMMING PERFORMANCE
Limit
Unit
Parameter
Symbol
Typ2
90
1
Max3
200
2
Sector Erase Time
TSE
TBE
TCE
TBP
TPP
ms
s
Block Erase Time
Chip Erase Time
10
7
30
30
5
s
Byte Programming Time ( for AAI program )
Page Programming Time
us
ms
1.5
Byte Programming Time – 1st byte4
( for page program )
TBP1
100
6
150
12
us
us
Byte Programming Time – after 1st byte4
( for page program )
TBP2
Chip Programming Time
Erase/Program Cycles1
Data Retention
50
100,000
20
100
s
-
-
Cycles
Years
Notes:
1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25°C, 3V.
3. Maximum values measured at 85°C, 2.7V.
4. For multiple bytes after first byte within a page, TBPN = TBP1 + TBP2 *N (typical) and TBPN = TBP1 + TBP2 *N (max), where N
= number of bytes programmed. TBP1 (typical) is also the recommended delay time before reading the status register after
issuing a page program instruction.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.4 25/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
