ESMT
F25L16PA (2S)
Table 3: F25L16PA Block Protection Table
Status Register Bit
Protected Memory Area
Protection Level
BP3
0
BP2
0
BP1
0
BP0
0
Block Range
None
Address Range
None
0
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
Bottom 1/2
Bottom 3/4
Bottom 7/8
Bottom 15/16
Bottom 31/32
All Blocks
0
0
0
1
Block 31
1F0000H – 1FFFFFH
1E0000H – 1FFFFFH
1C0000H – 1FFFFFH
180000H – 1FFFFFH
100000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 1FFFFFH
000000H – 0FFFFFH
000000H –17FFFFH
000000H –1BFFFFH
000000H – 1DFFFFH
000000H – 1EFFFFH
000000H – 1FFFFFH
0
0
1
0
Block 30~31
Block 28~31
Block 24~31
Block 16~31
Block 0~31
Block 0~31
Block 0~31
Block 0~31
Block 0~15
Block 0~23
Block 0~27
Block 0~29
Block 0~30
Block 0~31
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Block Protection (BP3, BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”.
BP3, BP2, BP1 and BP0 bits as long as WP is high or the
Block- Protection-Look (BPL) bit is 0. Chip Erase can only be
executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory
default setting for Block Protection Bit (BP3 ~ BP0) is 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
12/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
