ESMT
F25L16PA (2S)
Table 5: Device Operation Instruction - Continued
Bus Cycle 1~3
Max.
Freq
Operation
1
2
3
4
5
6
N
SIN SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT
Jedec Read ID
50MHz 9FH Hi-Z
~
X
8CH
X
21H
Hi-Z
X
15H
-
-
-
-
-
-
(JEDEC-ID) 9
00H Hi-Z
01H Hi-Z
X
X
8CH
14H
X
X
14H
8CH
-
-
-
-
Read ID (RDID) 11
90H Hi-Z
00H
Hi-Z
00H
100MHz
Notes:
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
3. One bus cycle is eight clock periods.
4. 4K byte Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH.
5. 32K byte Block Earse addresses: use AMS -A15, remaining addresses can be VIL or VIH
64K byte Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
6. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
9. The JEDEC-Read-ID is output first byte 8CH as manufacture ID; second byte 21H as memory type; third byte 15H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. A successful WRSR can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
13. Dual output data:
IO
IO
0
= (D
6
, D
4
, D
2
, D
0
), (D
6
, D
4
, D
2
, D
0
)
)
1
= (D
7
, D5
, D3
, D1
), (D
7
, D5
, D3
, D1
DOUT0
DOUT1
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4 15/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
