ESMT
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
•
•
•
•
•
•
•
•
Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Auto Address Increment (AAI) Programming is completed and
reached its highest unprotected memory address
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instructions
F25L08PA
Operation Temperature Condition -40°C~85°C
BUSY
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Auto Address Increment (AAI)
The Auto-Address-Increment-Programming-Status bit provides
status on whether the device is in AAI Programming mode or
Page Program mode. The default at power up is Page Program
mode.
Table 3: F25L08PA Block Protection Table
Protection Level
0
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
0
0
0
0
1
1
1
1
Status Register Bit
BP2
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protected Memory Area
Block Range
None
Block 15
Block 14~15
Block 12~15
Block 8~15
Block 0~15
Block 0~15
Block 0~15
Address Range
None
F0000H – FFFFFH
E0000H – FFFFFH
C0000H – FFFFFH
80000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as
WP
is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Block Protection Lock-Down (BPL)
WP
pin driven low (V
IL
), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP
pin is driven high (V
IH
), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date:
Jul. 2009
Revision: 1.3
6/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
