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F25L016A-100PAIG 参数 Datasheet PDF下载

F25L016A-100PAIG图片预览
型号: F25L016A-100PAIG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆( 2Mx8 ) 3V只有串行闪存 [16Mbit (2Mx8) 3V Only Serial Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 32 页 / 375 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L016A  
Operation Temperature condition -40°C~85°C  
9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .  
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 15H as memory  
capacity.  
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.  
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions  
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.  
Read (33 MHz)  
The Read instruction supports up to 33 MHz, it outputs the data  
starting from the specified address location. The data output  
stream is continuous through all addresses until terminated by a  
(wrap-around) of the address space, i.e. for 16Mbit density, once  
the data from address location 1FFFFFH had been read, the next  
output will be from address location 00000H.  
The Read instruction is initiated by executing an 8-bit command,  
low to high transition on CE . The internal address pointer will  
automatically increment until the highest memory address is  
reached. Once the highest memory address is reached, the  
address pointer will automatically increment to the beginning  
03H, followed by address bits [A23-A0]. CE must remain active  
low for the duration of the Read cycle. See Figure 2 for the Read  
sequence.  
CE  
MODE3  
1 2 3 4 5 6 7 8  
15 16  
23 24  
31 32  
39 40  
47 48  
55 56  
63 64  
70  
SCK MODE1  
ADD.  
MSB  
03  
ADD.  
ADD.  
SI  
MSB  
N
N+1  
DOUT  
N+2  
DOUT  
N+3  
DOUT  
N+4  
DOU T  
HIGH IMPENANCE  
SO  
DOUT  
MSB  
Figure 2 : READ SEQUENCE  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jul. 2008  
Revision: 1.2 11/32  
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