ESMT
48
47
2
:
32
31
1
:
16
15
0
:
0
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
030000H – 030FFFH
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
0
0
0
0
0
0
0
1
0
0
1
0
F25L008A
Operation Temperature condition -40
°C
~85
°C
Table2 : F25L008A Block Protection Table
Protection Level
0
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
0
0
0
0
1
1
1
1
Status Register Bit
BP2
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protected Memory Area
Block Range
None
Block 15
Block 14~15
Block 12~15
Block 8~15
Block 0~15
Block 0~15
Block 0~15
Address Range
None
F0000H – FFFFFH
E0000H – FFFFFH
C0000H – FFFFFH
80000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, P1, BP0 bits as long as
WP
is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP
pin driven low (V
IL
), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP
pin is driven high (V
IH
), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision:
1.2
4/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
