EN25P05
Power-up Timing
Figure 19. Power-up Timing
Table 7. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
Max.
Unit
µs
(1)
VCC(min) to CS# low
10
1
tVSL
(1)
Time delay to Write instruction
Write Inhibit Voltage
10
ms
V
tPUW
(1)
1
2.5
VWI
Note:
1.The parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
The Status Register contains 00h (all Status Register bits are 0).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
20
Rev. C, Issue Date: 2008/01/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
