EN25P05
Sector Erase (SE) (D8h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector
(see Table 2.a and Table 2.b) is a valid address for the Sector Erase (SE) instruction. Chip Select
(CS#) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 12.. Chip Select (CS#) must be driven High after the
eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle
(whose duration is t ) is initiated. While the Sector Erase cycle is in progress, the Status Register
SE
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP1, BP0)
bits (see Table 3.a and Table 3.b) is not executed.
Figure 12. Sector Erase Instruction Sequence Diagram
Bulk Erase (BE) (C7h)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the
instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 13.. Chip Select (CS#) must be driven High after the
eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle (whose duration
is t ) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to
BE
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP1, BP0) bits are 0. The Bulk
Erase (BE) instruction is ignored if one, or more, sectors are protected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
15
Rev. C, Issue Date: 2008/01/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
