EN25F20A
Table 1. Pin Names
Symbol
CLK
DI (DQ
0
)
DO (DQ
1
)
CS#
WP# (DQ
2
)
HOLD# (DQ
3
)
Vcc
Vss
NC
Pin Name
Serial Clock Input
Serial Data Input (Data Input Output 0)
*1
*1
Serial Data Output (Data Input Output 1)
Chip
Select
Write Protect (Data Input Output 2)
HOLD# pin (Data Input Output 3)
Supply Voltage (2.7-3.6V)
Ground
No Connect
*2
*2
Note:
1. DQ
0
and DQ
1
are used for Dual and Quad instructions.
2. DQ
2
~ DQ
3
are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ
0
, DQ
1
, DQ
2
, DQ
3
)
The EN25F20A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ
0
, DQ
1
, DQ
2
and DQ
3
) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ
3
) for Quad I/O operation.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ
2
) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
Elite Semiconductor Memory Technology Inc.
Rev. C, Issue Date: 2016/07/22
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
