ESMT
Pin Assignment
AD8256A
MCLK
PLLGND
PLLVDD
CLK_OUT
DVDD
DGND2
DGND1
N.C.
SDATA0
SDATA1
SDATA2
LRCIN
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
HPL
HPR
AGND
AVDD
PWMSA
DEF
SDA
SCL
SA1
SA0
ERROR
PD
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NAME
MCLK
PLLGND
PLLVDD
CLK_OUT
DVDD
DGND2
DGND1
N.C.
SDATA0
SDATA1
SDATA2
LRCIN
BCLK
VDDRB1
RB1
GNDR1
RA1
VDDRA1
VDDRA2
I
I
I
I
I
P
O
P
O
P
P
TYPE
DESCRIPTION
Master clock input
Ground for PLL
Supply for PLL
PLL output
Digital Power
Digital Ground2
Digital Ground1
No Connection
Serial audio data input 0
Serial audio data input 1
Serial audio data input 2
Left/Right clock input (Fs)
Bit clock input (64Fs)
Supply1 for right channel B
Right channel output1 (-)
Ground1 for right channel
Right channel output1 (+)
Supply1 for right channel A
Supply2 for right channel A
CHARACTERISTICS
Schmitt trigger TTL input buffer
I
P
P
O
P
P
P
(Note1)
TTL output buffer
(Note1)
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
(Note2)
(Note2)
(Note2)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
2/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
