ESMT
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RA2
GNDR2
RB2
VDDRB2
Re set
PD
ERROR
AD8256A
O
P
O
P
I
I
O
I
I
I
I
I
O
P
P
O
O
I
P
O
P
O
P
P
O
P
O
P
I
Right channel output2 (+)
Ground2 for right channel
Right channel output2 (-)
Supply2 for right channel B
Reset, low active
Power down, low active
ERROR output
I
2
C select address 0
I
2
C select address 1
I
2
C serial clock input
I
2
C serial data input
Default volume, 0=Mute, 1=Un-Mute
Half-bridge, sub-woofer channel output
Analog supply
Analog ground
Headphone right channel output
Headphone left channel output
Headphone detection
Supply2 for left channel B
Left channel output2 (-)
Ground2 for left channel
Left channel output2 (+)
Supply2 for left channel A
Supply1 for left channel A
Left channel output1 (+)
Ground1 for left channel
Left channel output1 (-)
Supply1 for left channel B
PLL Bypass
(Note2)
Schmitt trigger TTL input buffer
(Note2)
(Note2)
(Note2)
(Note2)
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Open-drain output
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer with
open-drain output
Schmitt trigger TTL input buffer
TTL output buffer
(Note1)
SA0
SA1
SCL
SDA
DEF
PWMSA
AVDD
AGND
HPR
HPL
HP-SPK
VDDLB2
LB2
GNDL2
LA2
VDDLA2
VDDLA1
LA1
GNDL1
LB1
VDDLB1
PLL_Byp
Note1：These pins provide the supply for digital PWM controller, headphone drivers, built-in PLL and
protection circuits except for loudspeaker short-circuit protection circuits.
Note2：These pins provide the supply for loudspeaker driver stages, which are known as “PVDD”.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
3/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
