ESMT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GNDL
USB/I
2
S
AD6255A
P
I
I
I
O
I
P
O
P
I/O
I/O
I
I
I
I
O
I
Ground for left channel
Low is USB mode, high is I
2
S mode
Mode selection bit 1
Mode selection bit 0
Crystal output
Crystal input
Ground
3.3V regulator output
5V supply voltage
USB data D-
USB data D+
Theater mode, high active
Volume down, low active
Volume up, low active
Power-down and mute of Class D
Error output
Reset signal
Schmitt trigger TTL input buffer
With internal pull-up resistor
With internal pull-up resistor
Schmitt trigger TTL input buffer
Open-Drain output
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
SEL1
SEL0
XO
XI
GND
REGO
VDD
USBDM
USBDP
THEATER
VOLDN
VOLUP
MUTE
ERROR
RESET
Note1: Must be strapped resistor 1M
Ω
to 3.3V(REGO) or GND. BCLK, LRCIN and
PDO
must be
strapped to GND. SDATAO is strapped by 1M
Ω
to GND when AD6255A’s volume/mute is
controlled by external button, otherwise strapped by 1M
Ω
to 3.3V when AD6255A is I
2
C slave
mode for SEL1 is logic LOW.
Absolute Maximum Ratings
Symbol
VDD
VDDL(R)
V
i
T
stg
T
a
Parameter
Supply for regulator input
Supply for Left (Right) Channel
Input Voltage
Storage Temperature
Ambient Operating Temperature
Voltage Difference between V
DDL
and V
DDR
Voltage Difference between V
DDL
(V
DDR
) and DVDD/AVDD
V
DDL
(V
DDR
) Power-on Voltage Ramp
Min
0
0
-0.3
-65
0
-1
-3
Max
5.5
5.5
3.6
150
70
1
3
0.2
Units
V
V
V
o
C
o
C
V
V
V/μs
Recommended Operating Conditions
Symbol
VDD
VDDL(R)
T
a
Parameter
Supply for regulator input
Supply for Driver Stage
Ambient Operating Temperature
Typ
4.5~5.5
3.0~5.0
0~70
Units
V
V
o
C
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2007
Revision: 1.3
3/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
