Figure 4
Capacitive Load
Figure 2
The PKF series has no maximum limit for capacitive load on the out-
put. The power module may operate in current limiting mode during
start-up, affecting the ramp-up and the start-up time. For optimum
start performance we recommend maximum 100 mF/A of IO. Connect
capacitors at the point of load for best performance.
Output Voltage Adjust (Vadj
)
Output voltage, VO, can be adjusted by using an external resistor.
Typical adjust range is 15%. If pin 8 and 9 are not connected to-
gether the output will decrease to a low value.To increase VO a resis-
tor should be connected between pin 8/9 and 17, and to decrease VO a
resistor should be connected between pin 8 and 9 (see fig. 4).
Parallel Operation
Paralleling of several converters is easily accomplished by direct
connection of the output voltage terminal pins. The load regulation
characteristic is specifically designed for optimal paralleling per-
formance. Load sharing between converters will be within 10%. It
is recommended not to exceed PO = n × 0.9 × POmax, where POmax is
the maximum converter output power and n the number of paralleled
converters, to prevent overloading any of the converters and thereby
decreasing the reliability performance.
Typical required resistor value to increase VO is given by:
R
adj = k1×(k2 – VO)/(VO – VOi), (kW)
where VO is the desired output voltage
VOi is the typical output voltage initial setting
and
k1=3.18
k1=3.18
k1=3.18
k2=3.86
k2=5.93
k2=8.05
PKF 5510
PKF 5611
PKF 5617
Current Limiting Protection (Ilim
)
The output power is limited at loads above the output current
limiting threshold (Ilim), specified as a minimum value.
Typical required resistor value to decrease VO is given by:
adj = k3 × (VOi –VO)/(VO – k4), (kW)
R
Synchronization (Sync)
where k3=13.0
k3=12.6
k4=2.75
k4=4.28
k4=5.95
PKF 5510
PKF 5611
PKF 5617
It is possible to synchronize the switching frequency to an external
symmetrical clock signal. The input is TTL-compatible and refer-
enced to the input pin 17.
k3=12.6
Characteristic
min
typ
max
unit
High level
Threshold level*)
Low level
2.2
1.2
0
6.5
2.2
0.4
1.5
688
V
V
1.7
V
Sink current
Sync. frequency
mA
kHz
520
*) Rise time <10ns
Input and Output Impedance
Both the source impedance of the power feeding and the load imped-
ance will interact with the impedance of the DC/DC power module.
It is most important to have the ratio between L and C as low as
possible, i.e. a low characteristic impedance, both at the input and
output, as the power modules have a low energy storage capability.
Use an electrolytic capacitor across the input if the source is larger
than 10 mH. Their equivalent series resistance together with the
capacitance acts as a lossless damping filter. Suitable capacitor values
are in the range 10–100 mF.
Figure 3
Voltage Margining
For voltage controlled margining e.g. at final test, the following
setup can be used. By increasing the control voltage V1 to +10 V the
output voltage decreases 5% of VOi, and by decreasing V1 to –10 V
the output voltage increases 5%.
12
EN/LZT 146 32 R1A (Replaces EN/LZT 137 27 R3) ©Ericsson Microelectronics, June 2000
ERICSSON [ ERICSSON ]
