PBM 3960/1
Electrical Characteristics
Electrical characteristics over recommended operating conditions.
Parameter
Ref.
Symbol fig Conditions
Min
Typ
Max
Unit
Logic Inputs
Reset logic HIGH input voltage
Reset logic LOW input voltage
Logic HIGH input voltage
Logic LOW input voltage
Reset input current
Input current, other inputs
Input capacitance
V
IHR
V
ILR
V
IH
V
IL
I
IR
I
I
3.5
0.1
2.0
V
SS
< V
IR
< V
DD
V
SS
< V
I
< V
DD
-0.01
-1
3
2
2
2
2
2
2
2
3
Valid for A0, A1
Valid for D0 - D7
60
60
70
0
0
0
50
80
6
V
O
= 2.4 V
V
O
= 0.4 V
From positive edge of WR.
outputs valid, C
load
= 120 pF
From positive edge of Reset to
outputs valid, C
load
= 120 pF
Reset open, V
Ref
= 2.5 V
9
-13
5
30
60
-5
100
150
0.8
1
1
V
V
V
V
mA
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
kΩ
mA
mA
ns
ns
Internal Timing Characteristics
Address setup time
t
as
Data setup time
t
ds
Chip select setup time
t
cs
Address hold time
t
ah
Data hold time
t
dh
Chip select hold time
t
ch
Write cycle length
t
WR
Reset cycle lenght
t
R
Reference Input
Input resistance
Logic Outputs
Logic HIGH output current
Logic LOW output current
Write propagation delay
Reset propagation delay
DAC Outputs
Nominal output voltage
Resolution
Offset error
Gain error
Endpoint nonlinearity
Differential nonlinearity
Load error
Power supply sensitivity
Conversion speed
t
DAC
R
Ref
I
OH
I
OL
t
pWR
t
pR
1.7
2
3
V
DA
7
7
7
5, 6
0
7
0.2
0.1
0.2
0.2
0.1
0.1
3
2
(V
DA
, unloaded - V
DA
, loaded)
R
load
= 2.5 kΩ, Code 127 to DAC
Code 127 to DAC
4.75 V < V
DD
< 5.25 V
For a full-scale transition to
±0.5
LSB
of final value, R
load
= 2.5 kohm, C
load
= 50 pF.
V
Ref
- 1LSB V
Bits
0.5
LSB
0.5
LSB
0.5
LSB
0.5
LSB
0.5
LSB
0.3
8
LSB
µs
3