PBL 386 50/2
hook and 1.3 VPeak on-hook. If a resistor
ROV is connected between the POV pin
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 11. The ROV and
corresponding VTRO (signal headroom)
are typical values for THD <1% and the
signal frequency 1000Hz.
Observe that the 4-wire output terminal
VTX can not handle more than 3.2 VPeak. So
if the gain 2-wire to 4-wire is -6.02dB,
6.4 VPeak is maximum also for the 2-wire
side. Signal levels between 6.4 and
12.8 VPeak on the 2-wire side can be han-
dled with the PTG shorted so that the gain
G2-4S become -12.04dB. Please note that
the 2-wire impedance, RR and the 4-wire to
4-wire gain has to be recalculated if the
PTG is shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 29 mA.
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 50/2 SLIC
reduce the dc line current when the chip
temperature reaches approximately
145°C and increases it again automati-
cally when the temperature drops.
Accordingly transmission is not lost
under high ambient temperature condi-
tions.
How to use POV:
1. Decide what overhead voltage(VTRO) is
needed. The POV function is only
needediftheoverheadvoltageexceeds
3.2 VPeak
2. In figure 11 the corresponding ROV for
the decided VTRO can be found.
3. If the overhead voltage exceeds
6.4 VPeak , the G2-4S gain has to be
changed to -12.04dB by connecting
the PTG pin to AGND. Please note
that the two-wire impedance, RR and
the 4-wire to 4-wire gain has to be
recalculated.
The detector output, DET, is forced to a
logic low level when the temperature
guard is active.
RFB
PBL 386 50/2
CTX
RTX
KR
-
PTG
VTX
-
0
+
+
RT
RRLY
HP
AGND
RSN
NC
RB
+12 V /+5V
RRX
0
CGG
DHP
CHP
NC
CODEC/
Filter
RF2
RR
RP2
RING
TIP
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
NC
REF
PLC
POV
PLD
VCC
NC
RREF
RLC
ROV
RLD
CRC
CTC
VB
OVP
RF1
RP1
PBL 386 50/2
DVB2
VB2
VB
VCC
VCC
DBB
RSG
CVB2
DVB
CVCC
DET
C1
CLP
ERG
CVB
R1
LP
RRT
DT
C2
R2
DR
C3
C1
C2
SYSTEM CONTROL
INTERFACE
R3
R4
SLIC No. 2 etc.
RESISTORS: (Values according to IEC E96 series)
CAPACITORS: (Values according to IEC E96 series)
OVP:
RSG
RLD
ROV
RLC
RREF
RR
= 0 Ω
1% 1/10 W
1% 1/10 W
CVB
CVB2
CVCC
CTC
CRC
CHP
CLP
CTX
CGG
C1
= 100 nF
= 150 nF
= 100 nF
= 2.2 nF
= 2.2 nF
= 47 nF
100 V 10%
100 V 10%
10 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
100 V 10%
63 V 10%
63 V 10%
Secondary protection ( e.g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
= 49.9 kΩ
= User programmable
= 32.4 kΩ
= 49.9 kΩ
= 11.5 kΩ
= 52.3 kΩ
= 32.4 kΩ
= 57.6 kΩ
= 52.3 kΩ
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
RT
= 150 nF
= 68 nF
NOTES:
RTX
RB
1. RP1 and RP2 may be omitted if DVB is in
place.
= 220 nF
= 330 nF
= 330 nF
RRX
RFB
R1
2. It is required to connect DHP between
terminal HP and ground if CHP >47nF.
Depending on CODEC / filter
C2
= 604 kΩ
= 604 kΩ
= 249 kΩ
= 280 kΩ
= 330 Ω
≥ 10 Ω
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
5% 2 W
DIODES:
DVB
R2
= 1N4448
= 1N4448
= 1N4448
R3
DVB2
R4
DBB
RRT
RP1, RP2
RF1, RF2
DHP
= 1N4448 (Note 2)
1% 1/10 W (Note 1)
= Line resistor, 40 Ω 1% match
Figure 12. Single-channel subscriber line interface with PBL 386 50/2 and combination CODEC/filter.
13
ERICSSON [ ERICSSON ]
