PBL 386 30/2
15
16
17
18
19
20
21
22
NU
C2
C1
DET
NC
VCC
PLD
POV
Pin
Not Used.
Must be connected to AGND.
C1 and C2 are digital inputs (internal pull-up) controlling the SLIC operating states.
Refer to section "Operating states" for details.
Detector
output. Active low when indicating loop detection and ring trip.
No
internal
Connection
+5 V power supply.
Programmable Loop Detector
threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
Programmable Overhead Voltage.
If pin is left open: The overhead voltage is internally set to min 2.7 V in
off-hook and min 1.1 V in On-hook. If a resistor is connected between this pin and AGND: the overhead
voltage can be set to higher values.
Prog. Line Current,
the current limit, reference C in figure 12, is programmed by a resistor connected from
this pin to AGND.
A
Reference,
49.9 kΩ, resistor should be connected from this pin to AGND.
No
internal
Connection
Receive Summing Node.
200 times the AC-current flowing into this pin equals the metallic (transversal)
AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node. A resistor should be connected from this pin to AGND.
Analog Ground, should be tied together with BGND.
Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG).
The two-wire impedance programming network connects between VTX and RSN.
23
24
25
26
PLC
REF
NC
RSN
27
28
AGND
VTX
SLIC Operating States
State
0
1
2
3
C2
0
0
1
1
C1
0
1
0
1
SLIC operating state
Open circuit
Ringing state
Active state
Not applicable
Active detector
-
Ring trip detector (active low)
Loop detector (active low)
-
Table 1. SLIC operating states.
9