PBL 385 71
9
(a)
R
A
3
9
(b)
C
A
R
A
C
A
3
R
A
9
(c)
C
A
3
(a),(c), (d)
C
B
R
B
attenuation
(a and b)
attn. = R
TI
//(R
TI
+R
A
)
no attn. = R
A
= 0
9
C
C
R
A
(d)
R
A
C
A
R
B
C
A
3
9
(e)
3
9
C
C
R
A
C
A
(f)
3
(b),(e)
big C
A
R
B
attn.without dc.
C
B
small C
A
R
B
C
B
(f)
attenuation
attn.without dc.
Figure 11. Possible network types between microphone amplifier and transmitter.
Receiver amplifier
The receiver amplifier consists of three
stages, the first stage being an input buffer
that renders the input a high impedance.
The second stage is a gain regulated diffe-
rential amplifier and the third stage a
balanced power amplifier. The power
amplifier has a differential output with low
DC- offset voltage, therefore a series
capacitor with the load is normally not
necessary. The receiver amplifier uses at
max. swing 4-6 mA peak. This current is
drawn from the +Line. The driving capa-
city of the power stage can be optimized by
connecting a resistor in series with the
earphone itself fig.12 b.). The gain and
frequency response is set at the input RI
with a RC-network. The receiver gain can
be regulated. The range of regulation
from the input to the output is 5
±
2 dB (19
to 24dB). The balanced earphone amplifier
can not be loaded to full (both current and
signal level ) single ended.The signal would
be distorded when returned to ground. A
methode is shown in fig.12 d. how to
connect a light load (5k ac. or DC wise) to
the output. It is preferred that both outputs
are loaded the same. The receiver has, as
a principal protection, two series diodes
anti parallel across its output to limit the
signal to the earphone and thus preven-
ting an acoustical shock. A resistor in
series with the output can very well be
used to increase the protection level. Note,
that the noise in the receiver is allways
transmitter noise that has been more or
less well balanced out by the side tone
network.
The RC - network (optional) at the
output is to stabilize against the inductive
load that an earphone represents.
(a)
(b)
(c)
(d)
PBL 38 571
-
+
Rx
+
15
PBL 38 571
PBL 38 571
15
15
+
-
Rx
+
+
16
+
-
Rx
+
16
(C)
Z
16
Z
(C)
Z > 5k
The capacitor C is optional
Gain regulation.
Both the receiver and transmitter are
gain regulated (line loss compensated).
There is a fixed default compensation on
the chip that can be adjusted or or set to
constant low gain mode. The input
impedance at the gain regulation pin 8 is
5.5k
±
20%. The default regulation pattern
is valid when the input is left open. Fig. 13
shows a typical transmitter or receiver
8
Figure 12. Receiver arrangements.
gain pattern versus line length. The
following will show, what to alter, to change
the look of the curve.
a). Adjustable with the divider R4,R5
for the transmitter and with R12 for the
receiver.
b). The attack point of the regulator is
adjusted with the divider R1,R2 (fig. 18) to
either direction, up or down, on the line
current axis.
c). The angle of elevation of the curve
is mainly set by the value of R6. If the DC-
characteristics is set according to the line
parameters and a correct value for R6 is
chosen the angle is mostly correct but it
can be adjusted with R6. The adjustement
will affect the DC-characteristics as well as
most of the other parameters. This is why
the DC- characteristic is set early in the
design phase.
ERICSSON [ ERICSSON ]
