PBL 3853
+L
TO
1
2
3
4
5
6
7
8
9
18 VDC
17 RI 2
16 RO
15 RI 1
14 -L
+L
1
2
3
4
20
19
18
VDC
RI2
TI
TO
TI
RO
RI1
-L
+C
+C
DCAC
GR
17
16
DCAC
GR
T2
5
6
13 MI 2
12 MI 1
11 MO
10 TM
15 MI 2
14
13
12
11
MI 1
MO
TM
T2
7
8
T1
T1
9
FE
FE
10
NC
NC
18 pin-DIP
20 pin-SO
Figure 5. Pin configuration.
Pin Description
DIP
SO
Symbol
1
2
3
4
5
6
7
8
9
1
+L
Output of the transmitter (+Line side)
2
TO
Output of the transmitter (side tone signal)
Input of the transmitter amplifier
3
TI
4
+C
The circuit supply (sinks ~ 0,3 mA)
Adjustment for DC-char. and AC imp. to line
Gain regulation starting point setting
5
DCAC
GR
T2
6
7
Output for transistor 2, active when voltage on the line is too low for VDC
Output for transistor 1, active when charging current into VDC’s reservoir capacitor
Feedback
8
T1
9
FE
10
11
12
13
14
15
16
17
18
19
20
NC
NC
TM
MO
MI 1
MI 2
-L
No connection
No connection
10
11
12
13
14
15
16
17
18
Transmitter mute input
Microphone amplifier output
Microphone amplifier inverting input
Microphone amplifier non inverting input
Negative terminal of the circuit
RI1
RO
RI 2
VDC
Receiver amplifier input (gain control)
Receiver amplifier output
Receiver amplifier input for cut-off, see page 7.
VDC supply terminal
5
ERICSSON [ ERICSSON ]
