PBL 3766
PLCC
DIP
Symbol
Description
11
8
DET
Detector output. Inputs C1 and C2 select one of the two detectors to be connected to the DET output. A
logic low level at the enabled (refer to E0) DET output indicates a triggered detector condition. The DET
output is open collector with internal pull-up resistor (approximately 15 kohms) to VCC.
C1 and C2 are TTL compatible inputs controlling the SLIC operating states. Refer to section
Control inputs for details.
Dc loop feed is programmed by one resistor connected from this pin to the receive summing node (RSN)
A decoupling capacitor, C
DC
, connected from RDC to GND removes noise and other ac signals from the
battery feed control loop.
No internal connection. Note 1.
Receive summing node. 1000 times the current (dc and ac) flowing into this pin equals the metallic
(transversal) current flowing from RINGX to TIPX. Programming networks for constant dc loop current,
two-wire impedance and receive gain connect to the receive summing node.
Refer to PLCC, terminal 6 description.
-5V power supply.
Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of one. The two-wire termina-
ting impedance programming network connects between VTX and RSN.
Tip side of ac/dc separation capacitor C
HP
. Other end of C
HP
connects to pin, HPR.
Ring side of ac/dc separation capacitor C
HP
. Other end of C
HP
capacitor connects to pin, HPT.
Loop current detector programming resistor R
D
connects from RD to VEE. An optional filter capacitor C
D
may be connected between terminal RD and ground. With the RD pin left open, the loop current detect
threshold is internally set to 8.0 mA. Refer to section Loop monitoring functions for additional information.
DT is the non-inverting ring trip comparator input. The inverting comparator input is internally connected
to V
EE
. With DT more negative than the inverting input, the detector output, DET, is at logic level low,
indicating off-hook condition. The ring trip network connects to the DT input.
Refer to PLCC, terminal 6 description.
No internal connection. Note 1.
TIPX
Sense
is internally connected to TIPX. TIPX
Sense
is used during manufacturing, but requires no
connection in SLIC applications, i.e. leave open.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relays).
12
13
14
9
10
11
C2
C1
RDC
15
16
-
12
NC
RSN
17
18
19
-
13
14
VBAT
VEE
VTX
20
21
22
15
16
19
HPT
HPR
RD
23
20
DT
24
25
26
27
28
-
-
-
21
22
VBAT
NC
TIPX
Sense
TIPX
RINGX
Notes
1.
Terminals marked NC are not internally connected to the chip. These terminals may be connected to ground for shielding.
4-9
ERICSSON [ ERICSSON ]
