Crystal oscillator
Epson Toyocom
SG / HG-8002 series_
Jitter specifications and characteristics chart
■
PLL-PLL connection
Because we use a PLL technology, there are a few cases that the jitter value will increase when SG-8002 is connected to another
PLL-oscillator.
In our experience, we are unable to recommend these products for the applications such as telecom carrier use or analog video
clock use. Please be careful checking in advance for these application (Jitter specification is Max.250 ps/CL=15 pF)
Jitter Specifications
Model
PT
/
PH
ST
/
SH
SC
/
PC
Supply
Voltage
5.0 V
±0.5
V
Peak to peak
3.3 V
±0.3
V
Cycle to cycle
Peak to peak
Jitter Item
Cycle to cycle
Specifications
150
ps Max.
200 ps Max.
200 ps Max.
250 ps Max.
200 ps Max.
250 ps Max.
Remarks
33 MHz
≤
f
0
≤
125
MHz, L_CMOS=15 pF
1.0
MHz
≤
f
0
< 33 MHz, L_CMOS=15 pF
33 MHz
≤
f
0
≤
125
MHz, L_CMOS=15 pF
1.0
MHz
≤
f
0
< 33 MHz, L_CMOS=15 pF
1.0
MHz
≤
f
0
≤
125
MHz, L_CMOS=15 pF
1.0
MHz
≤
f
0
≤
125
MHz, L_CMOS=15 pF
■
Remarks on noise management for power supply line
We do not recommend inserting filters or other devices in the power supply line as the counter measure of EMI noise reduction.
This device insertion might cause high-frequency impedance high in the power supply line and it affects oscillator stable drive.
When this measure is required, please evaluate circuitry and device behavior in the circuit and verify that it will not affect oscillation.
Start up time (0 % V
CC
to 90 % V
CC
) of power source should be more than
150
µs.
■
SG-8002 series Characteristics chart
50
40
I
CC
(mA)
30
20
10
0
50
40
I
_dis
(mA)
30
20
10
0
50
40
Symmetry (%)
I
_std
(
µ
A)
30
20
10
2.5
3.0 3.5 4.0 4.5 5.0
V
CC
(V)
5.5 6.0
20
40 60 80
100 120 140
Frequency(MHz)
Stand-by Current
20
40 60 80
100 120 140
Frequency(MHz)
Current consumption
(V
CC
=5.0V)
60
Symmetry (%)
55
50
45
40
0
60
Symmetry (%)
55
50
15
pF
50 pF
Symmetry 5.0 V CMOS Level
25 pF
3.0
Output Rise time (CMOS Level)
4.5 V
5.0 V
5.5 V
2.5
Rise time (ns)
15
pF
3.0 V
3.3 V
3.6 V
2.7 V
2.0
1.5
20
40 60 80
100 120 140
Frequency(MHz)
1.0
10 15
20 25 30 35 40 45
50 55
Disable Current
(V
CC
=5.0V)
Symmetry 3.3 V CMOS Level
3.0
30 pF
Load capacitance (pF)
Output Fall time (CMOS Level)
3.0 V
3.3 V
3.6 V
4.5 V
5.0 V
5.5 V
Fall Time (ns)
2.5
45
40
0
20
40 60 80
100 120 140
Frequency(MHz)
2.0
2.7 V
1.5
60
55
50
45
40
0
Symmetry 5.0V TTL Level
1.0
10 15
20 25 30 35 40 45
Load capacitance (pF)
50 55
25 pF
15
pF
2.0
Rise Time (ns)
1.5
1.0
Output Rise time (TTL Level)
4.5 V
5.0 V
5.5 V
20
40 60 80
100 120 140
Frequency(MHz)
10
2.0
Fall Time (ns)
Additional Value (mA)
Output load vs. Additional Current consumption
20
V
CC
=5.0 V
18
25 pF
16
14
50 pF
12
15
pF
10
30 pF
8
6
4
2
Voltage coefficient [
V
CC
vs I_dis,I_std ]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
I_dis(Va)=Times(Va)×I_dis(5.0V)
I_std(Va)=Times(Va)×I_std(5.0V)
15
20
25
Load capacitance (pF)
Output Fall time (TTL Level)
30
Times
1.5
4.5 V
5.0 V
5.5 V
1.0
0
20
40 60 80
100 120 140
Frequency(MHz)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
CC
(V)
10
15
20
25
Load capacitance (pF)
30
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