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EPC120-QFN16 参数 Datasheet PDF下载

EPC120-QFN16图片预览
型号: EPC120-QFN16
PDF下载: 下载PDF文件 查看货源
内容描述: 完全集成的隔光芯片,带有2线总线接口 [Fully integrated Light-Barrier Chips with 2-Wire Bus Interface]
分类和应用:
文件页数/大小: 27 页 / 550 K
品牌: EPC [ ESPROS PHOTONICS CORP ]
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epc120  
4. 2-Wire Bus  
The 2-wire bus and the power supply utilize the same two wires. The data is transmitted by modulating the current on the power-line. The  
modulated current, together with the resistor in the power supply, produce a voltage signal on the line. All devices receive this signal. The  
system is designed to operate with a line impedance of 50Ω (±5%). An inductor in parallel of the resistor or a DC regulator with a lowpass  
feedback shape the pulses and keep the the DC voltage drop over the resistor low. The required corner frequency of this L/R-filter is listed in  
the table below.  
The communication interface has been designed to be used for line lengths of up to 100m and with up to 1023 sensor devices. For line  
lengths of up to 3m it is possible to operate the line without termination2. Above this length the line has to be terminated by a resistor of 50Ω  
(±5%) which is equal to the line impedance and a capacitor of 100nF in series.  
The data rate on the 2-wire bus is set by the parameter DRATE. It also defines TSCANmin (refer to Chapter Error: Reference source not found on  
page Error: Reference source not found) and the required inductor according to Table 1. The maximum data rate allowed on the 2-wire bis is  
depending on the bus length. The longer the bus wire, the lower the data rate. Table 1 shows the possible bus wire length according to the  
data rate.  
DRATE  
k
Data Rate on the  
2-Wire Bus  
Minimal Data Rate  
Required on SPI  
Interface  
Corner  
Frequency L/R  
Inductor  
Bus Wire  
Length3  
00  
01  
10  
11  
8
4
2
1
250 kbit/s  
500 kbit/s  
1 Mbit/s  
300 kbit/s  
600 kbit/s  
1.2 Mbit/s  
2.4 Mbit/s  
0.5 MHz  
1 MHz  
2 MHz  
4 MHz  
16µH  
8µH  
4µH  
2µH  
12 … 100m  
6 … 12m  
3 … 6m  
≤ 3m  
2 Mbit/s  
Table 1: Data rate of the 2-wire communication  
The default value of DRATE is 00. The parameter DRATE has to be identical for all devices on one physical 2-wire bus.  
The SPI bus should be faster than the 2-wire bus, otherwise the communication does not work. Since the command length dependent on the  
command type, the delay time to the next command has to be adjusted to the previous command. The time delay can be calculated with the  
given data length in Table 7 on page 19.  
The parameter CDET defines the optimal signal amplitude for the receiver. The maximum rate at pin VDDR (5.5V) should not be exceeded  
and signals which are smaller than 70% of the recommended values are not detected.  
Since the command length is dependent on the command type, the delay time to the next command has to be adjusted to the previous  
command. The time delay can be calculated with the given data length in Table 7 on page 19. The data handling chain of the 2-wire  
communication channel is shown in Figure 6.  
Transmitter  
Receiver  
Command  
Data  
Command  
Data  
Original  
Message  
Received  
Message  
Parity Bits  
added  
Error Correction  
Manchester  
Decoder +  
Error Detection  
Manchester  
Encoder  
Current  
Sink  
Line  
Filter  
A/D  
Converter  
Figure 6: Data handling  
2
3
Dependent on the electro-mechanical design and the bus location of the edge, the termination network can be necessary. It is in the  
responsibility of the system designer that the data integrity on the bus is guaranteed. Data integrity can be tested by readout bus  
transmission errors. It is strongly recommended to do that during type qualification during EMI qualification tests .  
The effective length is dependent on the electro-mechanical design of the edge. The values in the table are indicative only.  
© 2011 ESPROS Photonics Corporation  
Characteristics subject to change without notice  
8
Datasheet epc12x - V2.1  
www.espros.ch