eorex
EU1010
underflow. It means that timer1 data will be loaded from T1BF0(06H) and T1BF1(07H) buffer after T1EN
bit is set as “1” or timer1 underflow.
Address
08H
bit7
T1EN
W
bit6
T1F
R/W
#
bit5
T1CK
R/W
#
bit4
PWM
W
bit3
#
bit2
bit1
bit0
Name
T1C
`Timer1 pre-scaler
Read or Write
Default Value
#
W
#
W
#
W
#
0
#
0
Note:
*T1EN : timer1 enable flag
T1EN = 1, enable timer1 start to down count;
T1EN = 0, stop timer1 down count. (when T1EN=0 and write data into T1BF0(06H) and
T1BF1(07H) , the data will be directly passed to timer1 counter.)
*T1F : timer1 underflow flag
T1F = 1, timer1 underflow;
T1F = 0, timer1 not underflow.
Bit2~bit0 are timer1 clock source selection bits. It must follow the setting as below.
bit2
0
bit1
0
bit0
0
Timer1 pre-scaler (FCLK1= )
FOSC/1
FOSC/2
FOSC/4
FOSC/8
FOSC/16
0
0
1
0
1
0
0
1
1
1
#
#
PWM Mode
Feb.2009
www.eorex.com
12/21
EOREX [ EOREX CORPORATION ]
