EM48BM1684LBB
AC Operating Test Characteristics (Continued)
(VDD=1.7 ~ 1.95V, TA=-25°C ~85°C)
-6
-7.5
Symbol
Parameter
Units
Min.
Max.
100k
Min.
Max.
ACTIVE to ACTIVE Command
Period (Note 6)
tRC
90
90
ns
ns
ACTIVE to PRECHARGE
Command Period (Note 6)
PRECHARGE to ACTIVE
Command Period (Note 6)
ACTIVE to READ/WRITE Delay
Time (Note 6)
tRAS
tRP
42
18
18
12
1
45
22.5
22.5
15
100k
ns
tRCD
tRRD
tCCD
ns
ACTIVE(one) to ACTIVE(another)
Command (Note 6)
ns
READ/WRITE Command to
READ/WRITE Command
1
CLK
Date-in to PRECHARGE
Command
tDPL
tBDL
2
1
2
1
CLK
CLK
Date-in to BURST Stop Command
Data-out to High
tROH
Impedance from
CL=3
3
3
CLK
PRECHARGE Command
tREF
tDAL
Refresh Time (8,192 cycle)
Data-in to ACTIVE command
64
64
ms
ns
33
37.5
* All voltages referenced to VSS.
Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of
the clock, as follows:
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole
number)
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge
command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held
high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command
must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required,
and these may be done before or after programming the Mode Register.
Nov. 2010
www.eorex.com
10/22
EOREX [ EOREX CORPORATION ]
