eorex
Features
Preliminary
EM48AM1684VBD
256Mb (4M
×
4Bank
×
16) Synchronous DRAM
Description
The EM48AM1684VBD is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
4Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TFBGA 54B 12mm x 8mm.
• Fully Synchronous to Positive Clock Edge
• Single 2.7V ~ 3.6V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
Ordering Information
Part No
EM48AM1684VBD-75F
EM48AM1684VBD-75FE
Organization
16M X 16
16M X 16
Max. Freq
133MHz @CL3
133MHz @CL3
Package
TFBGA -54B
TFBGA -54B
Grade
Commercial
Extend temp.
Pb
Free
Free
* EOREX reserves the right to change products or specification without notice.
Mar. 2008
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