EM48AM1684VTG
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each users
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed VDD + 0.3V on any of the input pins or VDD supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held
high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command
must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required, and these may be done before or after programming the Mode Register.
Jun. 2010
11/20
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EOREX [ EOREX CORPORATION ]
