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EM48AM1684VTG 参数 Datasheet PDF下载

EM48AM1684VTG图片预览
型号: EM48AM1684VTG
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB ( 4mA的?? 4Bankà ?? 16 )同步DRAM [256Mb (4M×4Bank×16) Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 20 页 / 480 K
品牌: EOREX [ EOREX CORPORATION ]
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EM48AMM1684VTG  
4. Operative Command Table (Continued) (Note 7)  
Current  
/CS /R /C /W  
Addr.  
Command  
Action  
Notes  
state  
H
L
L
L
L
L
L
L
L
H
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL  
NOP  
BST  
NopEnter row active after tDPL  
NopEnter row active after tDPL  
NopEnter row active after tDPL  
Write  
H
L
BA/CA/A10 READ/READA Start read, Determine AP  
BA/CA/A10 WRIT/WRITA New write, Determine AP  
recovering  
L
14  
9
H
H
L
H
L
BA/RA  
BA, A10  
X
ACT  
ILLEGAL  
L
PRE/PALL ILLEGAL  
REF/SELF ILLEGAL  
9
L
H
L
L
L
Op-Code  
X
MRS  
ILLEGAL  
NopEnter pre-charge after tDPL  
X
X
X
DESL  
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
H
L
H
H
L
H
L
X
X
NOP  
BST  
NopEnter pre-charge after tDPL  
NopEnter pre-charge after tDPL  
Write  
H
L
BA/CA/A10 READ/READA ILLEGAL  
BA/CA/A10 WRIT/WRITA ILLEGAL  
9,14  
9
recovering  
with AP  
L
H
H
L
H
L
BA/RA  
ACT  
ILLEGAL  
9
L
BA, A10  
PRE/PALL ILLEGAL  
REF/SELF ILLEGAL  
L
H
L
X
L
L
Op-Code  
MRS  
ILLEGAL  
X
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
DESL  
NopEnter idle after tRC  
H
L
NOP/ BST NopEnter idle after tRC  
READ/WRIT ILLEGAL  
Refreshing  
H
L
ACT/PRE/PALL ILLEGAL  
L
REF/SELF/MRS ILLEGAL  
X
H
H
H
L
X
H
H
L
DESL  
NOP  
BST  
Nop  
L
Nop  
Mode  
L
L
L
ILLEGAL  
Register  
Accessing  
X
X
READ/WRIT ILLEGAL  
X
ACT/PRE/PALL/  
ILLEGAL  
REF/SELF/MRS  
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge  
Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle.  
Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.  
All input buffers except CKE will be disabled.  
Note 9: Illegal to bank in specified states;  
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.  
Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.  
All input buffers except CKE will be disabled.  
Note 11: Illegal if tRCD is not satisfied.  
Note 12: Illegal if tRAS is not satisfied.  
Note 13: Must satisfy burst interrupt condition.  
Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
Note 15: Must mask preceding data which don't satisfy tDPL  
Note 16: Illegal if tRRD is not satisfied.  
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Jun. 2010  
18/20  
www.eorex.com  
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