EM488M1644VTD
____________________________________________
Current
/CS /R /C /W
Addr.
Command
Action
Notes
state
Write
H
L
L
L
L
L
L
L
L
H
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
Nop→ Enter row active after tDPL
Nop→ Enter row active after tDPL
Nop→ Enter row active after tDPL
recovering
H
L
BA/CA/A10 READ/READA Start read, Determine AP
BA/CA/A10 WRIT/WRITA New write, Determine AP
L
8
3
3
H
H
L
H
L
BA/RA
BA, A10
X
ACT
ILLEGAL
L
PRE/PALL ILLEGAL
REF/SELF ILLEGAL
L
H
L
L
L
Op-Code
X
MRS
ILLEGAL
Nop→ Enter pre-charge after tDPL
Write
X
X
X
DESL
recovering
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
X
X
NOP
BST
Nop→ Enter pre-charge after tDPL
Nop→ Enter pre-charge after tDPL
with AP
H
L
BA/CA/A10 READ/READA ILLEGAL
BA/CA/A10 WRIT/WRITA ILLEGAL
3.8
3
L
H
H
L
H
L
BA/RA
ACT
ILLEGAL
3
L
BA, A10
PRE/PALL ILLEGAL
REF/SELF ILLEGAL
L
H
L
X
L
L
Op-Code
MRS
ILLEGAL
Refreshing H
X
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
DESL
Nop→ Enter idle after tRC
L
L
L
L
H
L
NOP/ BST Nop→ Enter idle after tRC
READ/WRIT ILLEGAL
H
L
ACT/PRE/PALL ILLEGAL
L
REF/SELF/MRS ILLEGAL
Mode
H
X
H
H
H
L
X
H
H
L
DESL
NOP
BST
Nop
Register
L
Nop
L
L
L
ILLEGAL
X
X
READ/WRIT ILLEGAL
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Accessing
X
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states;Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don't satisfy tDPL
.
10. Illegal if tRRD is not satisfied.
15