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EM488M1644VTC
Pin Descriptions (Simplified)
Pin
CLK
/CS
CKE
Name
System Clock
Chip select
Clock Enable
Pin Function
Master Clock Input(Active on the Positive rising edge)
Selects chip when active
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
A0 ~ A11
Address
Row address (A0 to A11) is determined by A0 to A11 level at the
bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the pre-
charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
BA0, BA1
/RAS
/CAS
/WE
Bank Address
Row address strobe
Selects which bank is to be active.
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
Column address strobe Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
Write Enable
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
UDQM / LDQM Data input/output Mask DQM controls I/O buffers.
DQ0 ~ 15
Data input/output
DQ pins have the same function as I/O pins on a conventional
DRAM.
V
DD
/ V
SS
V
DDQ
/ V
SSQ
NC
Power supply / Ground V
DD
and V
SS
are power supply pins for internal circuits.
Power supply / Ground V
DDQ
and V
SSQ
are power supply pins for the output buffers.
No connection
This pin is recommended to be left No Connection on the device.
8
EOREX [ EOREX CORPORATION ]
